The conventional structure of an individual thin-film transistor (TFT) consists of two lateral electrodes for source and drain current collection or injection, modulated by a third gate electrode. The source and drain electrodes are usually conductors, such as silver, gold, copper, doped polymer, or conductive oxides such as indium tin oxide.
U.S. Pat. No. 8,283,655, issued to Chabinyc, et al., and entitled “Promoting Layered Structures with Semiconductive Regions or Subregions,” discloses structures, devices, arrays, and methods related to thin-film fabrication. Layered structures, channel regions, and light-interactive regions can include the same semiconductive polymer material, such as with an organic polymer.
Generally, TFT circuits are laid out by connecting individual TFTs and other elements with metal interconnect. In organic circuits, a pair of unipolar (i.e., both n-type or both p-type) TFTs is typically realized by laying out two separate TFTs and wiring them together. For example, in a series-connected stack configuration, the source of one TFT is wired to the drain of the other TFT with interconnect, generally formed in the drain or source metal layer. An issue with TFT circuits is the large area necessitated by low mobility and limitations of printing resolution and registration, where printing techniques are used.
Accordingly, there remains a need for an improved structure for TFTs that increases transistor density and reduces the area required for a circuit design. As has been observed with silicon semiconductor devices, higher densities inevitably lead to higher computing power. The promise of combining the higher computing power, as seen in silicon circuits, with the economic efficiencies of TFTs will ultimately lead to improved computing devices.